Google's new TPUs: two chips per package, a vault, no price announced

In short

• On 09/11/2026, Google adds TPU 8tx (confidential inference) and TPU 8i Max (massive context windows) to its eighth generation: model names whose letters Google doesn't explain. With the 8t and 8i from April, that makes four systems in one year, a first according to Google.
• The 8i Max puts two 8i chips in one package: twice the computing power, the built-in fast memory (SRAM) and the memory transfer speed of a TPU 8i, according to Google.
• No price, no availability date, no absolute performance figure for the two newcomers.

Google's 09/11 post: nearly 100 customers, four TPU systems in a year

I opened the post with one question: how much? It starts with history: TPUs, the chips Google designs for AI, were born more than a decade ago for its internal needs, including voice recognition and translation. Today they train and serve Gemini, power Google Cloud customers and can even be deployed in customers' own data centers. Google claims "nearly 100 customers", from frontier AI labs to trading firms and universities. We had already met these chips in Anthropic's roughly $19 billion in leases at TeraWulf, partly guaranteed by Google: as compute accelerators, the contract only allows Google-approved TPUs on site.

On 22/04/2026, Google had unveiled two chips of this generation: 8t for training (when the model learns) and 8i for inference (when it answers). Against the previous generation, the 09/11 post credits them with "up to 2.7 times better training performance" for 8t and, for 8i, "80% better inference price performance": about 1.8 times as much work for the same price, according to Google, not an 80% price cut. 2.7 times what? The baseline values are not given. In April, Google put its 80% more plainly: serving nearly twice the customer volume at the same cost.

If you remember April's "nearly 3x" for 8t: that was the compute performance of a whole pod (the large group of interconnected chips), not training performance. Two different measures.

A chip takes years, a system a few months

The most useful sentence in the post isn't a number: designing a chip means laying out billions of transistors on silicon, a multi-year job. A system is what you assemble around it: networking, storage, memory, security. Hence the promise of specialized supercomputers delivered "in a matter of months rather than years". The two newcomers are precisely new configurations of the April systems.

TPU 8tx: the vault that computes

Picture a bank (my example, Google doesn't mention any) that wants an AI to work on its clients' files. Normally, Google reminds us, data is encrypted when stored or sent over a network, but the computer has to unlock it in memory to process it. That is the moment 8tx targets: confidential inference means having a model answer while keeping sensitive data and the model itself protected and isolated by the hardware, even while in active use. Target customers: regulated enterprises and governments.

Under the hood: the TPU 8t chip, processors from manufacturer AMD (EPYC range), the regular processors that drive the chips, and the Boardfly network Google built for real-time reasoning. The promise: response times up to twice as short as on TPU 8t ("up to 2x lower latency"), according to Google, with a "near-zero performance penalty". Still no milliseconds. And, according to Google, you can fine-tune a model on your private data there without moving it to another cluster.

TPU 8i Max: two chips in a single package

The second one takes on the "memory wall". When dozens of AI agents work together across an entire codebase or hours of video, memory bandwidth quickly becomes the bottleneck, Google explains. Its answer fits in one sentence: put two 8i chips in the same package. The announced result, compared with a TPU 8i: twice the computing power, twice the SRAM (very fast memory built into the chip) and twice the data transfer speed to HBM memory (bandwidth, not capacity). And because it fits twice the silicon in the same rack footprint, a data center can deploy "significantly more computing power per square foot and per watt" (for the same floor space and the same power consumption). Significantly, as in how much? Not written.

What Google isn't saying yet

No price, no availability date for 8tx and 8i Max, no absolute performance figure. In April, 8t and 8i were promised for "later this year"; the 09/11 post does not say whether they have arrived.

My take, flagged as such: Google now sells assemblies as much as chips, and that's clever. But a vault with no price tag, I don't know yet who to recommend it to.

Key terms

• TPU (Tensor Processor Unit; tensors are the arrays of numbers AI models handle): a chip designed by Google for AI computing; Google offers it as systems (chips, networking, memory, host CPUs).
• Training / inference: training is when the model learns; inference is when it answers a request.
• Encryption: scrambling data with a code so it can't be read without the key.
• Confidential inference: having a model answer while data and model stay protected and isolated by the hardware, even during computation.
• Latency: the waiting time before the answer.
• Context window: how much text (or code, or video) a model keeps in view at once; Google talks about million-token scale, tokens being the word fragments a model reads.
• Rack: the metal cabinet where servers are stacked in a data center.
• Compute density: how much computing power fits in one rack; Google promises the 8i Max "the highest compute density per rack".
• SRAM, HBM: SRAM is very fast memory built into the chip; HBM (high-bandwidth memory) is fast memory stacked right next to it. The "memory wall" is when the chip sits waiting for its data.

Source sheet

• Google: post "Our newest TPUs: 8tx and 8i Max, built for the agentic era", signed by Amin Vahdat (SVP and Chief Technologist, AI and Infrastructure), published on 09/11/2026 at 13:00 UTC.
• Google: post on the eighth-generation TPUs (8t and 8i), published on 22/04/2026.
• Links: Google's post on TPU 8tx and 8i Max (09/11/2026) · Google's post on TPU 8t and 8i (22/04/2026)

Source passages

Pages read on 09/11/2026 around 17:38-17:40 UTC (dated copies in the article folder).

Show the 2 sources

Ref.	Quote (original language)	URL
S1↑1↑2↑3↑4↑5↑6+13	"Nov 09, 2026" ; "We’ve expanded our eighth generation TPU portfolio with TPU 8tx and TPU 8i Max, marking four new TPU systems in a single year." ; "TPUs are now a rapidly growing business with nearly 100 customers — including frontier labs, trading firms, retailers, universities, and more." ; "TPU 8t and 8i offer up to 2.7 times better training performance and 80% better inference price performance, respectively, versus our previous generation of TPUs." ; "This is the first time we have introduced four TPU systems in a single year." ; "We first designed TPUs more than a decade ago motivated by Google’s internal demands, including voice recognition and language translation." ; "allowing customers to deploy TPUs directly into their own data centers" ; "TPU 8i Max for massive context windows and the highest compute density per rack, and TPU 8tx for secure and confidential inference" ; "Designing a new chip means laying out billions of microscopic transistors on a silicon wafer in a multi-year process" ; "It’s built for regulated enterprises and governments" ; "the same low-latency Boardfly network we created for real-time reasoning" ; "fine-tune models using their private data [...] without needing to migrate sensitive data between separate clusters" ; "When dozens of AI agents work together across an entire software codebase or hours of video at once, memory bandwidth quickly becomes the bottleneck." ; "million-token context scale" ; "That approach allows us to deliver specialized supercomputers in a matter of months rather than years." ; "we have created two new configurations of these foundational systems" ; "Normally, data is encrypted when stored or sent over a network, but has to be unlocked in memory while a computer processes it. Built on the same silicon as TPU 8t and paired with 5th Generation AMD EPYC CPU hosts, TPU 8tx builds security directly into the hardware layer, keeping sensitive data and model weights protected and isolated even while in active use." ; "delivering up to 2x lower latency compared to TPU 8t with a near-zero performance penalty" ; "So we took two low-latency TPU 8i chips and combined them onto a single package." ; "delivering double the compute, double the SRAM and double the HBM bandwidth of TPU 8i" ; "because TPU 8i Max fits twice the silicon within the existing rack footprint, data centers can deploy significantly more computing power per square foot and per watt."	https://blog.google/innovation-and-ai/infrastructure-and-cloud/global-network/tpu-8i-max-and-8tx/
S2↑1↑2↑3↑4↑5	"Today at Google Cloud Next, we are introducing the eighth generation of Google's custom Tensor Processor Unit (TPU), coming soon with two distinct, purpose-built architectures for training and inference: TPU 8t and TPU 8i." ; "These innovations deliver 80% better performance-per-dollar compared to the previous generation, enabling businesses to serve nearly twice the customer volume at the same cost." ; "we have crafted a system that delivers nearly 3x the compute performance per pod over the previous generation" ; "Both chips will be generally available later this year" (post published on 22/04/2026)	https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/eighth-generation-tpu-agentic-era/